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IS42VM16400G 1m x 16bits x 4banks low power synchronous dram description these IS42VM16400G are low power 67,108,864 bits cmos synchro nous dram organized as 4 banks of 1,048,576 words x 16 bits. these products are offering fully synchronous operation and are referenced to a positive edge of the clock. all inputs and outputs are synchronized with the rising edge of the clock input. the data paths are internally pipelined to achieve high bandwidth. all input and output voltage levels are compatible with lvcmos. ? jedec standard 1.8v power supply. ? auto refresh and self refresh. ? all pins are compatible with lvcmos interface. ?4k refresh c y cle / 64ms. ? all inputs and outputs referenced to the positive edge of the system clock. ? data mask function by dqm. ? internal 4 banks operation features y/ ? programmable burst length and burst type. - 1, 2, 4, 8 or full page for sequential burst. - 4 or 8 for interleave burst. ? programmable cas latency : 2,3 clocks. ? programmable driver strength control - full strength or 1/2, 1/4 of full strength ? deep power down mode ? internal 4 banks operation . ? burst read single write operation. ? special function support. - pasr(partial array self refresh) - auto tcsr(temperature compensated self refresh) ? automatic precharge, includes concurrent auto precharge mode and controlled precharge. ? deep power down mode . copyright ? 2010 integrated silicon solution, inc. all rights reserv ed. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, prod ucts or services described herein. customers are advised to obtain the latest vers ion of this device specificat ion before relying on any publish ed information and before placing orders for products. ss f f f f 1 www.issi.com - dram@issi.com rev. a | july 2010 integrated s ilicon s olution, inc. does not recommend the use o f any o f its products in li f e support applications where the f ailure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect it s safety or effectiveness. products are not authorized for use in such applicat ions unless integrated silicon solution, inc. receives writt en assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon soluti on, inc is ade quately protec ted under the circumstances
IS42VM16400G figure1: 54ball fbga ball assignment a b c 1 2 3 4 5 6 7 8 9 vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq vddq dq0 vdd vssq dq2 dq1 vddq dq4 dq3 c d e f dq12 dq11 vssq dq10 dq9 vddq udqm clk cke vddq dq4 dq3 vssq dq6 dq5 /cas /ras /we dq8 nc vss vdd ldqm dq7 g h j nc a11 a9 a8 a7 a6 vss a5 a4 ba0 ba1 /cs a0 a1 a10 a3 a2 vdd [top view] 2 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G table2: pin descriptions pin pin name descriptions pin pin name descriptions clk system clock the system clock input. all other inputs are registered to the sdram on the rising edge clk. cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh. /cs chip select enable or disable all inputs except clk, cke and dqm. ba0 ba1 bkadd selects ba nk t o b e a ctiv a te d du rin g ras a ctivit y . ba0 ~ ba1 b an k add ress ba o b a a d du g a y selects bank to be read/written during cas activity. a0~a11 address row address : ra0~ra11 column address : ca0~ca7 auto precharge : a10 /ras, /cas, /we row address strobe, column address strobe, write enable ras, cas and we define the operation. refer function truth table for details. ctl ttbff i d d d ki tdti ldqm,udqm data input/output mask c on t ro l s ou t pu t b u ff ers i n rea d mo d e an d mas k s i npu t d a t a i n write mode. dq0~dq15 data input/output data input/output pin. vdd/vss power supply/ground power supply for internal circuits and input buffers. vddq/vssq data output power/ground power supply for output buffers. nc no connection no connection. 3 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G figure3: functional block diagram bank d tcsr clock generator clk cke extended mode register bank d row decoder bank c row decoder pasr row address buffer & refresh counter mode register bank b row decoder bank a row dec o address control l command d e column address buffer & counter /cs /ras / cas o der sense amplifier column decoder & latch circuit l ogic e coder burst counter / /we data control circuit dqm latch circuit input & output dq input & output buffer 4 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G figure4: simplified state diagram self refresh extended mode register set idle cbr refresh power down mode register set act ref mrs deep power down row active down active power down read write cke cke pr e down cke cke read write read a write a read suspend read a suspend write suspend write a suspend cke cke cke cke read write e suspend suspend cke cke pre- charge power on precharge 5 www.issi.com - dram@issi.com rev. a | july 2010 automatic sequence manual input
IS42VM16400G a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 figure5: mode register definition ba0 ba1 a11 wb 0 cas latency bt burst length address bus 0 1 2 3 4 5 6 10987 11 mode register (mx) 00 0 0 12 0 13 m9 write burst mode 0 burst read and burst write 1 burst read and single write m3 burst type 0sequential 1interleave m6 m5 m4 cas latency 000 reserved 001 - 010 2 011 3 100 reserved 101 reserved 1 1 0 reserved m2 m1 m0 burst length m3 = 0 m3 = 1 000 1 1 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved burst type accesses within a given burst may be programmed to be either seque ntial or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column add ess as sho n in table 3 1 1 0 reserved 111 reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 111full pagereserved note: m13/m12(ba1/ba0) must be set to ?0/0? to select mode register (vs. the extended mode register) add r ess , as sho w n in table 3 . table 3: burst definition burst length starting column address order of access within a burst sequential interleaved a2 a1 a0 2 00-1 0-1 11-0 1-0 note : 1. for full-page accesses: y = 256 2. for a burst length of two, a1-a7 select the block- of-two burst; a0 selects the starting column within the 4 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 11 3-0-1-2 3-2-1-0 000 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 001 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2 - 3 - 4 - 5 - 6 - 7 - 0 - 1 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 block. 3. for a burst length of four, a2-a7 select the block- of-four burst; a0-a1 select the starting column within the block. 4. for a burst length of eight, a3-a7 select the block-of-eight burst; a0-a2 select the starting column within the block. 5. for a full-page burst, the full row is selected and a0-a7 8 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 011 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 100 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 101 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 110 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 111 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n=a0 7 c n , c n +1. c n +2, selec t the startin g column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a0-a7 select the unique column to be accessed, and mode register bit m3 is ignored. 6 www.issi.com - dram@issi.com rev. a | july 2010 full page n=a0 - 7 (location 0-255) c n +3, c n +4? ?c n -1, c n ... not supported
IS42VM16400G figure6: extended mode register a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 ba0 ba1 0 pasr address bus extended mode register (ex) 0 1 2 3 4 5 6 10987 11 0 00 0 ds 0 12 0 0 1 13 e2 e1 e0 self refresh coverage 0 0 0 all banks 001two banks (ba1=0) 0 1 0 one bank (ba1=ba0=0) 0 1 1 reserved 1 0 0 reserved e6 e5 driver strength 00 full strength 0 1 1/2 strength 1 0 1/4 strength 11 reserved 1 0 1 half of one bank (ba1=ba0=0, row address msb=0) 1 1 0 quarter of one bank (ba1=ba0=0, row address 2 msb=0) 1 1 1 reserved note: e13/e12(ba1/ba0) must be set to ?1/0? to select extend mode register (vs. the base mode register) 7 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G in general, this 64mb sdram (1m x 16bits x 4banks) is a multi-ba nk dram that operates at 1.8v and includes a synchronous functional description interface (all signals are registered on the positive edge of the c lock signal, clk). each of the 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16-bits read and write accesses to the sdram are burst oriented; accesse s start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0-ba1 select the bank, a0-a11 select the row). the address bits (ba0-ba1 select the bank, a0-a7 select the column) registered coincident with the read or write command are u sed to select the starting column location for the burst access. pi t l ti th sdram t b iitili d th fll i ti id dtild if ti i di p r i or t onorma l opera ti on, th e sdram mus t b e i n iti a li ze d . th e f o ll ow i n g sec ti ons prov id e d e t a il e d i n f orma ti on cover i n g d ev i ce initialization, register definition, command descriptions and device operation. power up and initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. once power is applied to vdd and vddq(simu ltaneously) and the clock is stable(stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to issuing any command other than a command inhibit or nop cke must be held high during the entire initialization period until the precharge command other than a command inhibit or nop . cke must be held high during the entire initialization period until the precharge command has been issued. starting at some point during this 100s period a nd continuing at least through the end of this period, command inhibit or nop commands should be applied. once the 100s delay has been satisfied with at least one comma nd inhibit or nop command having been applied, a precharge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. onceintheidlestate,twoautorefreshcyclesmustbeperformed.aftertheautorefreshcyclesarecomplete,thesdramis ready for mode register programming. because the mode registe r will power up in an unknown state, it should be loaded prior to applying any operational command . and a extended mode register set command will be issued to program specific mode of self applying any operational command . and a extended mode register set command will be issued to program specific mode of self refresh operation(pasr). the following these cycle s, the low power sdram is ready for normal operation. register definition mode register the mode register is used to define the specific mode of operation of the sdram. this definition includes the selection of a burst length, a burst type, a cas latency, an operating mode and a write burst mode. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power mode register command and will retain the stored information until it is programmed again or the device loses power . mode register bits m0-m2 specify the burst length, m3 specifies th e type of burst (sequential or interleaved), m4-m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies th e write burst mode, and m10-m12 should be set to zero. m13 should be set to zero to prevent extended mode register. themoderegistermustbeloadedwhenallbanksareidle,andthec ontroller must wait the specified time before initiating the subsequent operation. violating either of these re quirements will result in unspecified operation. extended mode register the extended mode register controls the functions beyond those controlled by the mode register. these additional functions are special features of the batram device. they include part ial array self refresh (pasr) and driver strength (ds). the extended mode register is programmed via the mode register set command and retains the stored information until it is programmed again or the device loses power. theextendedmoderegistermustbeprogrammedwithm7throughm11setto?0?.theextendedmoderegistermustbeloadedwhen all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requir ements results in unspecified operation. 8 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G burst length read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in figure 1. the burst length determines the maximum number of column locations that can be accessed for a given read or write command burst length determines the maximum number of column locations that can be accessed for a given read or write command . burst lengths of 1, 2, 4 or 8 locations are available for both the sequential a nd the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjuncti on with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incom patibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is e ffectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a7 when the burs t len g th is se t to two ; b y a2-a7 when the burs t len g th is se t to four ; and b y a3-a7 when the burs t len g th is se t to ei g h t . t he g ; y g ; y g g remaining (least significant) address bit(s) is (are) used to select t he starting location within the block. full-page bursts wrap within the page if the boundary is reached. bank(row) active the bank active command is used to activate a row in a specified bank of the device. this command is initiated by activating cs ,ras and deasserting cas, we at the positive edge of the clock. the value on the ba0-ba1 selects the bank, and the value on the a0-a11se lects the row. this row remains active for column access until a precharge command is issued to that bank. read and write operations can only be initiated on this activated bank after the minimum trcd time is passed from the activate command. read the read command is used to initiate the burst read of data. th is command is initiated by activating cs, cas, and deasserting we , ras at the positive edge of the clock. ba0-ba1 input select the bank, a0-a7 address inputs select the starting column location. the va lue on input a10 determines whether or not auto precharge is used. if auto precharge is selected the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain active for subsequent accesses. the length of bur st and the cas latency will be determined by the values programmed during the mrs command. write the write command is used to initiate the burst write of data. this command is initiated by activating cs, cas, we and deassert ing ras at the positive edge of the clock ba0 - ba1 input select the bank a0 - a7 address inputs select the starting column location the value on at the positive edge of the clock . ba0 - ba1 input select the bank , a0 - a7 address inputs select the starting column location . the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected the row being accessed will be precha rged at the end of the write burst; if auto precharge is not selected, the row will remain active for subsequent accesses. 9 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of d h l b h lk f d d lk d d h l outpu t d ata. th e l atency can b ese t to two or t h ree c l oc k s. i f areadcomman d is re g istere d a t c l oc k e dg en,an d t h e l atency is m clocks, the data will be available by clock edge n+ m. the dqs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n+ m. for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in figure 7. reserved states should not be used as unknown operation or incompatibility with future versions may result. clk command nop nop t0 t1 t2 t3 read figure7: cas latency dq dout tlz toh tac cas latency=2 clk t0 t1 t2 t3 t4 clk command dq nop nop dout tlz toh tac cas latency=3 nop read operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved don?t care undefined for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation o r incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programme d via m0-m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write acce sses are single-location (nonburst) accesses. 10 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G table4: command truth table function cken-1 cken /cs /ras /cas /we dqm addr a10 note command inhinit (nop) h x h x x x x x no operation (nop) h x l h h h x x mode register set h x l l l l x op code 4 extended mode register set h x l l l l x op code 4 active (select bank and activate row) hxllhhx bank/row read h x l h l h l/h bank/col l 5 read with autoprecharge h x l h l h l/h bank/col h 5 write h x l h l l l/h bank/col l 5 write with autoprecharge h x l h l l l/h bank/col h 5 precharge all banks h x l l h l x x h prechar g e selected bank h x l l h l x bank l g burst stop h h l h h l x x auto refresh h h l l l h x x 3 self refresh entry h l l l l h x x 3 self refresh exit l h hx x x xx2 lh h h h x x x precharge power down entry h l h x x x xx lh h h precharge down exit l h hx x x xx lh h h clock suspend entry h l hx x x xx lv v v clock suspend exit l h x x x deep power down entry h l l h h l x x 6 deep power down exit l h x x x note : 1. cken is the logic state of cke at clock edge n; cken-1 was the state of cke at the previous clock edge. h: high level, l: low level, x: don't care, v: valid 2. exitin g self refresh occurs by asynchronously brin g in g cke from low to hi g h and will put the device in the all banks idle state once txsr is met. command inhibit or nop commands should be issued on any clock edges occuring during the txsr period. a minimum of two nop commands must be provided during txsr period. 3. during refresh operation, internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 4. a0-a11 define op code written to the mode register, and ba1/ ba0 must be issued ?0/0? in the mode register set, and ?1/0? in the extended mode register set. 5. dqm ?l? means the data write/ouput enable and ?h? means the write inhibit/output high-z. write dqm latency is 0 clk and read 11 www.issi.com - dram@issi.com rev. a | july 2010 dqm latency is 2 clk. 6. standard sdram parts assign this command sequence as burst terminate. for bat ram parts, the burst terminate command is assigned to the deep power down function.
IS42VM16400G table5: function truth table command current state command action note /cs /ras /cas /we ba a0-a11 description l l l l op code mode register set set the mode register 14 l l l h x x auto or self refresh start auto or self refresh 5 l l h l ba x precharge no operation l l h h ba radd bkai activate the specified idle l l h h ba r ow add . b an k a ct i vate activate the specified bank and row l h l l ba col add./ a10 write/writeap illegal 4 l h l h ba col add./ a10 read/readap illegal 4 l h h h x x no operation no operation 3 h x x x x x device deselect no operation or power down 3 row active llll op code mode re g ister se t illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge precharge 7 l l h h ba row add. bank activate illegal 4 l h l l ba col add./a10 write/write ap start write : optional ap(a10=h) 6 sta t read optional l h l h ba col add./a10 read/read ap sta r t read : optional ap(a10=h) 6 l h h h x x no operation no operation h x x x x x device deselect no operation l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 termination burst : read llhlba x prechar g e termination burst : start the precharge l l h h ba row add. bank activate illegal 4 l h l l ba col add./a10 write/writeap termination burst : start write(ap) 8,9 l h l h ba col add./a10 read/read ap terimination burst : start read(ap) 8 l h h h x x no operation continue the burst l h h h x x no operation continue the burst h x x x x x device deselect continue the burst 12 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G table5: function truth table command current state command action note /cs /ras /cas /we ba a0-a11 description l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 ll hlba x precharge termination burst : start the precharge 10 l l h h ba row add. bank activate illegal 4 write l l h h ba row add. bank activate illegal 4 l h l l ba col add./a10 write/writeap termination burst : start write(ap) 8 l h l h ba col add./a10 read/readap terimination burst : start read(ap) 8,9 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst read with auto precharge ll l l op code mode re g ister se t illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add./a10 write/writeap illegal 12 l h l h ba col add./a10 read/readap illegal 12 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst write with l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,12 with auto precharge l l h h ba row add. bank activate illegal 4,12 l h l l ba col add./a10 write/writeap illegal 12 l h l h ba col add./a10 read/readap illegal 12 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst 13 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G table5: function truth table current command action note state action note /cs /ras /cas /we ba a0-a11 description pechaging l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 ll hlba x precharge no operation : bank(s) idle after trp l l h h ba row add. bank activate illegal 4,12 p r echa r ging l h l l ba col add./ a10 write/writeap illegal 4,12 l h l h ba col add./ a10 read/readap illegal 4,12 l h h h x x no operation no operation : bank(s) idle after trp h x x x x x device deselect no operation : bank(s) idle after trp l l l l op code mode register set illegal 13,14 row activating l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,11,12 l h l l ba col add./a10 write/write ap illegal 4,12 l h l h ba col add./a10 read/read ap illegal 4,12 no operation : row l h h h x x no operation no operation : row active after trcd h x x x x x device deselect no operation : row active after trcd l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,13 write recovering l l h h ba row add. bank activate illegal 4,12 l h l l ba col add./a10 write/writeap start write : optional ap(a10=h) l h l h ba col add./a10 read/read ap start write : optional ap(a10=h) 9 l h h h x x no operation no operation : row active after tdpl h x x x x x device deselect no operation : row active after tdpl 14 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G table5: function truth table current command current state a ction note /cs/ras/cas/weba a0-a11 description write recovering with l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,13 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add / a10 write/writeap illegal 412 with auto precharge l h l l ba col add . / a10 write/writeap illegal 4 , 12 l h l h ba col add./ a10 read/readap illegal 4,9,12 l h h h x x no operation no operation : precharge after tdpl h x x x x x device deselect no operation : precharge after tdpl l l l l op code mode register set illegal 13,14 refreshing l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 13 l l h h ba row add. bank activate illegal 13 l h l l ba col add./a10 write/write ap illegal 13 l h l h ba col add./a10 read/read ap illegal 13 l h h h x x no operation no operation : idle fc l h h h x x no operation a f ter tr c h x x x x x device deselect no operation : idle after trc l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 13 l l h h ba row add bank activate illegal 13 mode register accessing l l h h ba row add . bank activate illegal 13 l h l l ba col add./a10 write/writeap illegal 13 l h l h ba col add./a10 read/read ap illegal 13 l h h h x x no operation no operation : idle after 2 clock cycle h x x x x x device deselect no operation : idle after 2 clock cycle 15 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G note : 1hlihihllil xd't babkadd apatp h 1 . h : l o gi c high , l : l o gi c l ow, x : d on 't care, ba : b an k add ress, ap : a u t o p rec h ar g e. 2. all entries assume that cke was active during the preceding clock cycle. 3. if both banks are idle and cke is inactive, then in power down cycle 4. illegal to bank in specified states. function may be legal in the bank indicated by bank address, depending on the state of that bank. 5. if both banks are idle and cke is inactive, then self refresh mode. 6. illegal if trcd is not satisfied. 7. illegal if tras is not satisfied. 8. must satisfy burst interrupt condition. 9. must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. must mask preceding data which don't satisfy tdpl. 11. illegal if trrd is not satisfied 12. illegal for single bank, but legal for other banks in multi-bank devices. 13. illegal for all banks. 14. mode register set and extended mode regist er set is same command truth table except ba. 16 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G table6: cke truth table current cke command ai n current state a ct i on n ote prev cycle current cycle /cs/ras/cas/weba a0-a11 self refresh hxxxxxxxinvalid 2 lhhxxxxx exit self refresh with device deselect 3 lhlhhhx x exit self refresh with no operation 3 refresh l h l h h l x x illegal 3 l h l h l x x x illegal 3 l h l l x x x x illegal 3 l l x x x x x x maintain self refresh hxxxxxxxinvalid 2 l h h x x x x x power down mode exit, all banks idle 3 power down l h banks idle 3 lh hhx x lhl l x x x x illegal 3 xlxx x xxlx x l l x x x x x x maintain power down mode hxxxxxxxinvalid 2 deep power down l h x x x x x x deep power down mode exit 6 l l x x x x x x maintain deep power down mode h h h x x x refer to the idle state section of the current state truth table 4 hhlhxx 4 hhllhx 4 all banks idle h h l l l h x x auto refresh h h l l l l op code mode register set 5 h l h x x x refer to the idle state section of the current state truth table 4 hllhxx 4 hlllhx 4 hllllhxxentry self refresh 5 h l l l l l op code mode register set l x x x x x x x power down 5 any state other than listed h h x x x x x x refer to operations of the current state truth table h l x x x x x x begin clock suspend next cycle l h x x x x x x exit clock suspend next 17 www.issi.com - dram@issi.com rev. a | july 2010 listed above l h x x x x x x exit clock suspend next cycle l l x x x x x x maintain clock suspend
IS42VM16400G note : 1. h: logic high, l: logic low, x: don't care 2. for the given current state cke mu st be low in the previous cycle. 3. when cke has a low to high transition, the clock and other in puts are re-enabled asynchronous ly. when exiting power down mod e, a nop (or device deselect) command is required on the first positive edge of clock after cke goes high. 4. the address inputs depend on the command that is issued. 5. the precharge power down mode, the self refresh mode, and the mode register set can only be entered from the all banks idle state. 6. when cke has a low to high transition, the cloc k and other inputs are re-enabled asynchronously. when exiting deep power down mode, a nop (or device deselect) comma nd is required on the first positive edge of clock after cke goes high and is maintained for a minimum 100usec high and is maintained for a minimum 100usec . 18 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G table7: absolute maximum rating parameter symbol rating unit ambient temperature (industrial) t a -40 ~ 85 c ambient temperature (commercial) 0 ~ 70 storage temperature t stg -55 ~ 150 c voltage on any pin relative to vss v in , v out -1.0 ~ 2.6 v voltage on vdd relative to vss vdd, vddq -1.0 ~ 2.6 v short circuit output current i os 50 ma short circuit output current i os 50 ma power dissipation p d 1w note : stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any ot her conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. table8: capacitance (t a =25 c, f=1mhz, vdd=1.8v) parameter pin symbol min max unit input capacitance clk c i1 24pf a0~a11, ba0~ba1, cke, /cs, /ras, /cas, /we, ldqm, udqm c i2 24pf data in p ut / out p ut ca p acitance d q 0~d q 15 c io 35 p f p/ p p qq io p table9: dc operating condition (voltage referenced to vss=0v, t a = -40 ~ 85 c) parameter symbol min typ max unit note power supply voltage vdd 1.70 1.8 1.95 v vddq 170 18 195 v 1 vddq 1 . 70 1 . 8 1 . 95 v 1 input high voltage v ih 0.8 x vddq - vddq+0.3 v 2 input low voltage v il -0.3 0 0.3 v 3 output high voltage v oh 0.9 x vddq - - v i oh = -0.1ma output low voltage v ol --0.2vi ol = +0.1ma input leakage current i li -1 - 1 ua 4 note : 1. vddq must not exceed the level of vdd 2. vih(max) = vddq+1.5v ac. the overshoot voltage duration is 3ns. 3. vil(min) = -1.0v ac. the overshoot voltage duration is 3ns. 4. any input 0v vin vddq. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. output leakage current i lo -1.5 1.5 ua 5 19 www.issi.com - dram@issi.com rev. a | july 2010 5. dout is disabled, 0v vout vddq.
IS42VM16400G table10: ac operating condition (t a = -40 ~ 85 c, vdd = 1.70v~1.95v, vss=0v) pt sbl t uit p arame t e r s ym b o l t yp u n it ac input high/low level voltage v ih / v il 0.9 x vddq / 0.2 v input timing measurement reference level voltage v trip 0.5 x vddq v input rise / fall time t r / t f 1 / 1 ns output timing measuremen t reference level voltage v outref 0.5 x vddq v output load capacitance for access time measurement c l 30 pf output 500 vddq output 50 vtt=0.5 x vddq z0 = 50 30pf output 30pf z0 50 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G table11: dc characteristic (dc operating conditions unless otherwise noted) pt s ttc diti speed uit nt p arame t e r s ym t es t c on diti on u n it n o t e -75 -10 operating current icc1 burst length=1, one bank active, trc trc(min) iol = 0 ma 50 45 ma 1 precharge standby current in power down mode icc2p cke vil(max), tck = 10ns 0.3 ma icc2ps cke & clk vil(max), tck = 0.3 icc2n cke vih(min), /cs vih(min), tck = 10ns input signals are changed one time during 2 clks 8 prechar g e standby current in non power down mode input signals are changed one time during 2 clks . ma icc2ns cke vih(min), clk vil(max), tck = input signals are stable. 1 active standby current in power down mode icc3p cke vil(max), tck = 10ns 5 ma icc3ps cke & clk vil(max), tck = 1 active standby current icc3n cke vih(min), /cs vih(min), tck = 10ns input signals are changed one time during 2 clks. 15 ma in non power down mode ma icc3ns cke vih(min), clk vil(max), tck = input signals are stable. 6 burst mode operating current icc4 tck>tck(min), iol = 0 ma, page burst all banks activated, tccd = 1 clk 55 50 ma 1 auto refresh current (4k cycle) icc5 trc trfc(min), all banks active 75 70 ma 2 pasr tcsr 85 c 350 self refresh current icc6 cke 0.2v ua 4 banks 45 c 180 2 bank 85 c 310 45 c 160 1 bank 85 c 290 45 c 150 deep power down mode current icc7 30 ua deep power down mode current icc7 30 ua note : 1. measured with outputs open. 2. refresh period is 64ms. 21 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G table12: ac characteristic (ac operation conditions unless otherwise noted) - 75 - 10 paramete r sym 75 10 unit note min max min max clk cycle time cl = 3 tck3 7.5 1000 10 1000 1 cl = 2 tck2 10 10 access time from clk (pos. edge) cl = 3 tac3 6 8 2 cl = 2 tac2 8 8 clk high-level width tch 2.5 2.5 3 clk low-level width tcl 2.5 2.5 3 ns cke setup time tcks 2.0 2.0 cke hold time tckh 1.0 1.0 /cs, /ras, /cas, /we, dqm setup time tcms 2.0 2.0 /cs, /ras, /cas, /we, dqm hold time tcmh 1.0 1.0 address setup time tas 2.0 2.0 address hold time tah 1.0 1.0 data-in setup time tds 2.0 2.0 data - in hold time tdh 10 10 data in hold time tdh 1 . 0 1 . 0 data-out high-impedance time from clk (pos.edge) cl = 3 thz3 6 8 4 cl = 2 thz2 8 8 data-out low-impedance time tlz 1.0 1.0 data-out hold time (load) toh 2.5 2.5 data-out hold time (no load) tohn 1.8 1.8 active to precharge command tras 45 100k 40 100k precharge command period trp 22.5 24 bk bk d active b an k a to active b an k a comman d trc 67.5 64 5 active bank a to active bank b command trrd 15 20 active to read or write delay trcd 22.5 30 read/write command to read/write command tccd 1 1 clk 6 write command to input data delay tdwd 0 0 6 data-in to precharge command tdpl 15 20 ns 7 data-in to active command tdal 37.5 40 7 dqm to data high-impedance during reads tdqz 2 2 6 clk dqm to data mask during writes tdqm 0 0 6 load mode register command to active or refresh command tmrd 2 2 8 data-out to high-impedance from precharge command cl = 3 troh3 3 3 6 cl = 2 troh2 2 2 last data-in to burst stop command tbdl 1 1 6 last data-in to new read/write command tcdl 1 1 6 cke to clock disable or power-down entry mode tcked 1 1 clk 9 clk cke to clock enable or power-down exit setup mode tped 1 1 9 refresh period (4,096 rows) tref 64 64 ms auto refresh period trfc 67.5 70 ns 5 exit self refresh to active command txsr 67.5 70 5 transition time tt 0.5 1.2 0.5 1.2 22 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G note : 1. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, including tdpl, and precharge commands). cke may be used to reduce the data rate. 2. tac at cl = 3 with no load is 5.5ns and is guaranteed by design. access time to be measured with input signals of 1v/ns edge rate, from 0.8v to 0.2v. if tr > 1ns, then (tr /2-0.5)ns should be added to the parameter. 3. ac characteristics assume tt = 1ns. if tr & tf > 1ns, then [(tr+tf)/2-1]ns should be added to the parameter. 4. thz defines the time at which the output achieves the open circuit condition; it is not a reference to voh or vol. the last valid data element will meet toh before going high-z. 5. parameter guaranteed by design. a. target values listed with alternative values in parentheses. b trfc t b l th l t trc 1 clk b . trfc mus t b e l ess th an or equa l t o trc + 1 clk txsr must be less than or equal to trc+1clk 6. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 7. timing actually specified by tdpl plus trp; clock(s ) specified as a reference only at minimum cycle rate 8. jedec and pc100 specify three clocks. 9. timing actually specified by tcks; clock(s) specified as a reference only at minimum cycle rate. 10. a new command can be given trc after self refresh exit. 23 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G special operation for low power consumption t e m pe r atu r e co m pe n sated se l f r e fr es h epeatue co pe sated se ees temperature compensated self refresh allows the controller to pro gram the refresh interval during self refresh mode, according to the case temperature of the low power sdram device. this allows great power savings during self refresh during most operating temperature ranges. only during extreme temperatures would the controller have to select a tcsr level that will guarantee data during self refresh. every cell in the dram requires refreshing due to the capacitor losing its charge over time. the refresh rate is dependent on temperature. at higher temperatures a capacitor loses charge quick er than at lower temperatures, requiring the cells to be refreshed more often. historically, during self refresh, the refresh rate h as been set to accommodate the wor st case, or highest temperature range expected. thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. this temperature compensated refresh rate will save pow er when the dram is operating at normal temperatures. partial array self refresh for further power savings during self refresh, the pasr feature allows the controller to select the amount of memory that will be refreshed during self refresh. the refresh options are all bank s;all four banks, two banks;bank a and b, one bank;bank a, half of one bank;1/2 of bank a, quarter of one bank;1/4 of bank a. write and read commands can still occur during standard operation, but only the selected banks will be refreshed during self r efresh. data in banks that are disabled will be lost. deep power down deep power down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of the devices. data will not be retained once the device enters deep power down mode. this mode is entered by having all banks idle then /cs and /we held low with /ras and /cas held high at the rising edge of the clock, whileckeislow.thismodeisexitedbyassertingckehigh. 24 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G figure7: deep power down mode entry clk cke /cs / ras precharge if needed deep power down entry trp / /cas /we don?t care figure8: deep power down mode exit clk cke /cs /ras /cas /we 100 s trp trfc 100 s trp trfc deep power down exit all banks precharge auto refresh mode register set extended mode register set new command auto refresh don?t care 25 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G 2 007 10/17/ 2 o utline package o 26 www.issi.com - dram@issi.com rev. a | july 2010
IS42VM16400G ordering information ? vdd = 1.8v configuration frequency (mhz) speed (ns) order part no. package 4mx16 133 7.5 IS42VM16400G-75bli 54-ball bga, lead-free industrial range: (-40 o c to +85 o c) 27 www.issi.com - dram@issi.com rev. a | july 2010

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